Generally, the process for manufacturing integrated circuits on a silicon wafer substrate typically involves deposition of a thin dielectric or conductive film on the wafer using oxidation or any of a variety of chemical vapor deposition processes; formation of a circuit pattern on a layer of photoresist material by photolithography; placing a photoresist mask layer corresponding to the circuit pattern on the wafer; etching of the circuit pattern in the conductive layer on the wafer; and stripping of the photoresist mask layer from the wafer. Each of these steps, particularly the photoresist stripping step, provides abundant opportunity for organic, metal and other potential circuit-contaminating particles to accumulate on the wafer surface.
In the semiconductor fabrication industry, minimization of particle contamination on semiconductor wafers increases in importance as the integrated circuit devices on the wafers decrease in size. With the reduced size of the devices, a contaminant having a particular size occupies a relatively larger percentage of the available space for circuit elements on the wafer as compared to wafers containing the larger devices of the past. Moreover, the presence of particles in the integrated circuits compromises the functional integrity of the devices in the finished electronic product. Currently, mini-environment based IC manufacturing facilities are equipped to control airborne particles much smaller than 1.0 μm, as surface contamination continues to be of high priority to semiconductor manufacturers. To achieve an ultra-clean wafer surface, particles must be removed from the wafer, and particle-removing methods are therefore of utmost importance in the fabrication of semiconductors.
The most common system for cleaning semiconductor wafers during wafer processing includes a series of tanks which contain the necessary cleaning solutions and are positioned in a “wet bench” in a clean room. Batches of wafers are moved in sequence through the tanks, typically by operation of a computer-controlled automated apparatus. Currently, semiconductor manufacturers use wet cleaning processes which may use cleaning agents such as deionized water and/or surfactants. Other wafer-cleaning processes utilize solvents, dry cleaning using high-velocity gas jets, and a megasonic cleaning process, in which very high-frequency sound waves are used to dislodge particles from the wafer surface. Cleaning systems which use deionized (DI) water currently are widely used in the industry because the systems are effective in removing particles from the wafers and are relatively cost-efficient. Approximately 4.5 tons of water are used for the production of each 200-mm, 16-Mbit, DRAM wafer.
A conventional KAIJO (trademark) PRS wet bench cleaning chamber, in use, is generally indicated by reference numeral 10 in cross-section in FIG. 1, and a longitudinal sectional view of the wet bench cleaning chamber 10 is shown in FIG. 2. The wet bench cleaning chamber 10 is typically used to rinse acid residue from wafers after the wafers are subjected to etching or other processing, for example. Typical uses for the chamber 10 include SPM cleaning, APM cleaning, PRS (photoresist stripping) cleaning and M2 etch/cleaning, for example. The chamber 10 includes chamber walls 12 that define a chamber interior 14 which receives multiple wafers 16. The chamber 10 typically includes a top opening 15, above which is disposed a pair of parallel overhead shower tubes 18, each of which is provided with multiple, adjacent nozzle openings 19. A pair of elongated, parallel bottom shower tubes 20, each provided with multiple adjacent nozzle openings 21, is provided in the bottom of the chamber interior 14. A wafer boat or other wafer support (not illustrated) removably contained in the chamber interior 14 typically holds up to fifty of the semiconductor wafers 16 in horizontally-adjacent relationship to each other, with the nozzle openings 19 of the respective overhead shower tubes 18 directed toward the upper edge portions of the wafers 16 and the nozzle openings 21 of the respective bottom shower tubes 20 directed toward the lower edge portions of the wafers 16.
In use, the overhead shower tubes 18 and the bottom shower tubes 20 are each connected to a source (not illustrated) of DI (deionized) water. In a quick dump rinse cycle, DI water 22 flows into a water inlet end 18a of each overhead shower tube 18 and into a water inlet end 20a of each bottom shower tube 20. The DI water flows from the overhead shower tubes 18 and the bottom shower tubes 20 through the nozzle openings 19 and 21, respectively, in a DI water spray 24 at a water flow rate of typically about 4,000-5,000 1/hr. Each nozzle opening 19, 20 ejects and disperses the DI water toward the wafers 16 in a relatively narrow-angled DI water spray 24, indicated by the dashed lines in FIGS. 1 and 2. Accordingly, the pressurized DI water spray 24 ejected from each nozzle opening 19, 21 is sufficiently wide to flow across the surfaces of typically about four consecutive, horizontally-spaced wafers 16, such that the wafers 16 are showered with the DI water sprays 24 and potential circuit-contaminating particles (not illustrated) are dislodged and removed from the upper and lower surfaces of the showered wafers 16.
One of the limitations inherent in the conventional DI water cleaning chamber or system 10 is that the DI water sprays 24 tend to progressively decrease in intensity along each overhead shower tube 18 from the water inlet end 18a thereof and along each bottom shower tube 20 from the water inlet end 20a thereof. This is due to progressively decreasing water pressure from the inlet ends 18a, 20a to the opposite ends of the respective shower tubes 18, 20. Therefore, the nozzle openings 19, 21 typically fail to provide a uniform spread of the DI water spray 24 along the surfaces of all of the wafers 16 in the chamber interior 14. Consequently, some of the wafers 16, particularly those closest to the inlet end 18a of each overhead shower tube 18 and the inlet end 20a of each bottom shower tube 20, are sprayed in a sufficient manner to rinse most or all of the acid, chemicals and particles from the surfaces of those wafers 20, whereas other wafers 16, particularly those furthest away from the inlet end 18a of each overhead shower tube 18 and the inlet end 20a of each bottom shower tube 20, remain inadequately sprayed by the DI water sprays 24. Thus, some of the acids and/or chemicals, as well as potential wafer-contaminating particles, remain on the surfaces of these inadequately-showered wafers 16.
Another problem frequently encountered in use of the conventional wet bench cleaning chamber 10 is that the wafers 16 tend to inadvertently shift in the chamber interior 14 as they are sprayed by the DI water sprays 24. Moreover, because the top opening 15 typically remains uncovered by a lid or cover during rinsing of the wafers 16, droplets of acids or other chemicals or particles being washed from the wafers 16 may become airborne and contaminate other wafer processing equipment in the vicinity of the chamber 10. Accordingly, a rinsing lid is needed for thorough rinsing of all semiconductor wafers in a wet bench cleaning chamber.
An object of the present invention is to provide a rinsing lid for a wet bench used in the rinsing of chemicals and/or particles from semiconductor wafers.
Another object of the present invention is to provide a multi-purpose rinsing lid which is suitable for a KAIJO (trademark) wet bench used in the rinsing of semiconductor wafers.
Still another object of the present invention is to provide a rinsing lid for a wet bench cleaning chamber, which rinsing lid is capable of thoroughly and uniformly rinsing multiple semiconductor wafers in the chamber.
Yet another object of the present invention is to provide a rinsing lid for a wet bench cleaning chamber, which rinsing lid is capable of retaining and substantially preventing or limiting inadvertent shifting of semiconductor wafers in the chamber during wet clean rinsing of the wafers.
Still another object of the present invention is to provide a rinsing lid for preventing splashing of acids, chemicals or particles from a wet bench cleaning chamber during wet clean rinsing of the wafers in the chamber.
A still further object of the present invention is to provide a rinsing lid for a wet bench cleaning chamber, which rinsing lid facilitates substantially uniform DI water pressure along the entire length of the lid as the water is sprayed from the lid for the uniform and thorough rinsing of wafers in the chamber.